Analog circuit cell array and analog integrated circuit

ABSTRACT

An analog circuit cell array includes a plurality of transistor cell arranged in an array. Each of the transistor cells includes a first source region, a first channel region, a common drain region, a second channel region, and a second source region arranged in sequence one adjacent to another; and a first gate electrode and a second gate electrode formed on the first channel region and the second channel region, respectively, and wherein the first gate electrode and the second gate electrode are connected together for use, and the first source region and the second source region are connected together for use.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is based upon and claims the benefit of priority of theprior Japanese Patent Application No. 2008-305100, filed on Nov. 28,2008, the entire contents of which are incorporated herein by reference.

FIELD

The embodiments discussed herein are related to an analog circuit cellarray and an analog integrated circuit formed by using an analog circuitcell array.

BACKGROUND

It is known to use a gate array in order to produce a digital integratedcircuit having a desired digital circuit with a short lead time. A gatearray is a chip on which a large number of basic cells, such astransistors and logic circuit elements, are arranged in an array. Byforming an interconnection pattern thereon that matches a user desireddigital circuit, the desired digital integrated circuit can be easilyproduced.

FIG. 1 is a diagram illustrating an example in which an interconnectionpattern is formed to interconnect four basic cells in a gate array. Inthe example of FIG. 1, two PMOS basic cells PMOSC1 s and two NMOS basiccells NMOSC1 s are arranged in close proximity to each other. Each PMOSbasic cell PMOSC1 has a P-type diffusion region PREG1 and twopolysilicon gates POLYGs formed on the PREG1. A P-type transistor drainregion DRAIN is formed between the two POLYGs, and P-type transistorsource regions SOURCEs are formed on the outer sides of the two POLYGs.That is, two PMOS transistors can be formed within this basic cell. EachNMOS basic cell NMOSC1 has an N-type diffusion region NREG1 and twopolysilicon gates POLYGs formed on the NREG1. An N-type transistor drainregion DRAIN is formed between the two POLYGs, and N-type transistorsource regions SOURCEs are formed on the outer sides of the two POLYGs.That is, two transistors can be formed within this basic cell. An N-typediffusion region NREG1 is formed is formed between the adjacent PMOSC1s, while a P-type diffusion region PREG1 is formed between the adjacentNMOSC1 s. The gate electrodes POLYGs, drain regions DRAINs, sourceregions SOURCEs, and inter-device diffusion regions PREG1, NREG1 of therespective basic cells PMOSC1 s and NMOSC1 s are interconnected by metalinterconnect lines METAL1 s and contacts CONT1 s.

A large number of basic units comprising such PMOSC1 s and NMOSC1 s arearranged in an array.

In the example of FIG. 1, two transistors can be formed in each of thebasic units PMOSC1 s and NMOSC1 s, but in an alternative example, onlyone transistor can be formed. The two transistors in each basic unit maybe used as transistors that perform the same operation in order todouble the driving capability, but alternatively, they can be configuredas two independent transistors. When using the transistors to performthe same operation, the drain region is common to the transistors, andthe two gate electrodes and the two source regions, respectively, areelectrically connected to each other. On the other hand, whenconfiguring them as two independent transistors, at least either the twogate electrodes or the two source regions are not electrically connectedto each other. In this way, the two transistors in each of the basicunits PMOSC1 s and NMOSC1 s are basically formed on the assumption thatthey are used independently of each other.

Gate arrays for digital circuits are well known, and will not bediscussed in detail here.

In recent years, it has been desired to increase the level ofintegration of analog circuits and to produce them with a short leadtime.

A digital circuit need only output or operate with a binary signalhaving a level falling within a predetermined range and representing a 0or a 1, and a circuit that operates properly can be easily produced ifmanufacturing errors are held within prescribed limits. On the otherhand, in analog circuits, analog signal values such as voltage valuesand current values directly affect the circuit operation and output. Asa result, analog circuits have had the problem that they are susceptibleto differences in device characteristics caused by manufacturing errors.It has therefore been common practice to design each individual analogcircuit according to the desired specification and to make adjustmentsat the manufacturing stage to achieve the production of the desiredcircuit.

In analog circuits, transistor characteristics differ according to thelocation of placement, due to such factors as ion implantation profilesand oxide film thickness profiles during manufacturing. A layout schemecalled common centroid layout is known for compensating for suchdifferences in characteristics. For example, if there is a difference inthe characteristics of two transistors forming a differential pair in adifferential amplifier, the error of the analog circuit increases;therefore, the two transistors forming such a differential pair arearranged in a common centroid configuration.

FIG. 2 is a diagram illustrating a common centroid layout example of adifferential pair of P-type transistors. The first P-type transistorPMAD1 forming one of the differential pair transistors comprises PMAD1Aand PMAD1B, and the second P-type transistor PMAD2 forming the otherdifferential pair transistor comprises PMAD2A and PMAD2B. PMAD1A andPMAD1B are arranged diagonally opposite each other, and PMAD2A andPMAD2B are also arranged diagonally opposite each other, the fourtransistors thus forming the vertices of a rectangle. The source regionsof the four P-type transistors PMAD1A, PMAD1B, PMAD2A, and PMAD2B areconnected together by metal interconnect lines NDSA and NDSB on firstand second layers, respectively, contacts CONT1 s, and plated-throughholes VIA1 s. The drain regions of the two P-type transistors PMAD1A andPMAD1B are connected to a first output via metal interconnect linesNDD1A and NDD1B, contacts CONT1 s, and plated-through holes VIA1 s. Thedrain regions of the two P-type transistors PMAD2A and PMAD2B areconnected to a second output via metal interconnect lines NDD2A andNDD2B, contacts CONT1 s, and plated-through holes VIA1 s. The gateelectrodes of the two P-type transistors PMAD1A and PMAD1B are connectedto a first input via a metal interconnect line IMOP1 and contacts CONT1s. The gate electrodes of the two P-type transistors PMAD2A and PMAD2Bare connected to a second input via a metal interconnect line IPOP1 andcontacts CONT1 s.

When the two transistors forming the differential pair are each formedfrom two transistors and arranged in a common centroid configuration, asillustrated in FIG. 2, the difference in the characteristics of the twotransistors forming the differential pair can be reduced by compensatingfor the effects of such factors as ion implantation profiles and oxidefilm thickness profiles.

Another factor known to adversely affect transistor matching is theantenna effect.

The antenna effect refers to a phenomenon in which, during a process(fabrication process) using a plasma for the fabrication of a MOStransistor, an electrical stress is applied to the gate oxide film ofthe MOS transistor because of the presence of electric charges in theplasma, leading to a reliability problem or causing the characteristicsof the MOS transistor to change. When processing the metal interconnectline connected to the gate oxide film, the metal interconnect line beingprocessed acts as an antenna and gathers electric charges, which candamage the gate oxide film; therefore, this phenomenon is generallycalled the antenna effect.

It is pointed out that, due to the electric charges gathered by theantenna (the metal interconnect line connected to the gate) during theprocessing of the metal interconnect line in the plasma process, thethreshold voltage Vth of the MOS transistor changes, and matchingbetween the MOS transistors forming a differential pair degrades due tounevenness in the antenna effect.

To alleviate the stress applied to the MOS transistor due to the antennaeffect, a method is known in the prior art that inserts a diode calledan antenna diode into the gate node of the MOS transistor to beprotected.

The antenna diode acts as a current discharge path during the processingof the metal interconnect line in the plasma process, and has thefunction of preventing possible damage to the gate oxide film. Duringnormal operation after the manufacture, this diode is reverse biased sothat it has hardly any effect on the operation, though it induces asmall amount of leakage current and an increase in capacitance and area.

It is known that the threshold voltage Vth of a MOS transistor changeswhen an interconnect line is present above the channel of the transistorthan when it is not.

Broken bonds known as dangling bonds exist at the interface between thechannel and gate oxide film of the MOS transistor, because the crystalstructure abruptly changes across the interface. Since the danglingbonds act as carrier traps, it is desirable to terminate the danglingbonds with hydrogen. If a metal interconnect line is present directlyabove the channel, it may prevent hydrogen from reaching the channelinterface in the annealing step which works to terminate the danglingbonds with hydrogen at the end of the fabrication process. It istherefore desirable that no interconnect lines be provided on MOStransistors that need matching. Otherwise, between the transistors thatneed matching, the entire structure including the interconnect lineabove the channel of the MOS transistor must be formed in the samegeometry.

Related Documents

Japanese Laid-open Patent Publication No. H08-97387

Japanese Laid-open Patent Publication No. H11-8319

Japanese Examined Patent Application Publication No. H07-28013

Japanese Laid-open Patent Publication No. 2001-177357

Hyungcheol Shin, Zhi-Jian Ma and Chenming Hu, “Impact of Plasma ChargingDamage and Diode Protection On Scaled Thin Oxide,” in Proc. IEEEInternational Electron Device Meeting, pp. 18.3.1-18.3.4, 1993.

Donggun Park, Chenming Hu, Scott Zheng, and Nguyen Bui, “A Full-ProcessDamage Detection Method Using Small MOSFET and Protection Diode,” IEEEELECTRON DEVICE LETTERS, VOL. 17, NO. 12, pp. 563-565, DECEMBER 1996.

Li-Da Huang, Xiaoping Tang, Hua Xiang, D. F. Wong, and I-Min Liu, “APolynomial Time-Optimal Diode Insertion/Routing Algorithm for FixingAntenna Problem,” IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OFINTEGRATED CIRCUITS AND SYSTEMS, VOL. 23, NO. 1, pp. 141-147, JANUARY2004.

Hans Tuinhout, Marcel Pelgrom, Red Penning de Vries, Maart en Vertregt,“Effects Of Metal Coverage on MOSFET Matching,” in Proc. IEEEInternational Electron Device Meeting, pp. 29.3.1-29.3.4, 1996.

SUMMARY

According to an aspect of the embodiments, an analog circuit cell arraycontains a plurality of transistor cells arranged in an array, andenables a desired analog circuit having a high level of integration tobe produced with a short lead time by forming an interconnection patternaccording to the circuit specification. Each transistor cell includes: afirst source region, a first channel region, a common drain region, asecond channel region, and a second source region arranged in sequenceone adjacent to another; and a first gate electrode and a second gateelectrode formed on the first channel region and the second channelregion, respectively, and wherein the first gate electrode and thesecond gate electrode are connected together for use, and the firstsource region and the second source region are connected together foruse.

The object and advantages of the embodiments will be realized andattained by means of the elements and combination particularly pointedout in the claims.

It is to be understood that both the foregoing general description andthe following detailed description are exemplary and explanatory and arenot restrictive of the invention, as claimed.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a diagram illustrating an example of the configuration andinterconnect layout of a digital circuit gate array according to theprior art;

FIG. 2 is a diagram illustrating a layout example in which a transistorpair in an operational amplifier circuit is arranged in a commoncentroid configuration;

FIG. 3 is a diagram illustrating an arrangement example of PMOS basiccells and NMOS basic cells in an analog circuit cell array according toan embodiment;

FIG. 4 is a diagram illustrating an arrangement example of gatepolysilicon and diffusion layer in a PMOS basic cell in the analogcircuit cell array according to the embodiment;

FIG. 5 is a diagram a configuration example of the PMOS basic cells inthe analog circuit cell array according to the embodiment;

FIG. 6 is a diagram a configuration example of the PMOS basic cells inthe analog circuit cell array according to the embodiment;

FIGS. 7A and 7B are diagrams explaining interconnect regions formed ineach PMOS basic cell in the analog circuit cell array according to theembodiment;

FIG. 8 is a diagram explaining interconnect regions formed in the analogcircuit cell array according to the embodiment;

FIG. 9 is a diagram illustrating a circuit example of a regulatorcircuit related to the embodiment;

FIG. 10 is a diagram illustrating a circuit example of a bandgap circuit(BGR circuit) contained in the regulator circuit;

FIG. 11 is a diagram explaining the relationship between the offsetvoltage and output voltage of the bandgap circuit (BGR circuit);

FIG. 12 is a diagram illustrating a circuit example of an operationalamplifier contained in the bandgap circuit (BGR circuit);

FIGS. 13A and 13B are diagrams explaining an antenna effect;

FIGS. 14A and 14B are diagrams illustrating an example of an antennadiode for preventing the antenna effect;

FIG. 15 is a diagram illustrating a prior art layout example of theantenna diode;

FIG. 16 is a diagram illustrating one example of a cross-sectionalstructure of the antenna diode;

FIG. 17 is a diagram illustrating an operational amplifier and anantenna diode circuit implemented using the analog circuit cell arrayaccording to the embodiment;

FIG. 18 is a diagram illustrating an example of layout at a first metalinterconnect level in which a P-type transistor pair in the operationalamplifier of FIG. 17, arranged in a common centroid configuration, andantenna diodes are implemented using the analog circuit cell arrayaccording to the embodiment;

FIG. 19 is a diagram illustrating an example of layout up to a secondmetal interconnect level in which the P-type transistor pair in theoperational amplifier of FIG. 17, arranged in a common centroidconfiguration, and the antenna diodes are implemented using the analogcircuit cell array according to the embodiment;

FIG. 20 is a diagram illustrating an example of layout up to the secondmetal interconnect level in which an N-type transistor pair in theoperational amplifier of FIG. 17, arranged in a common centroidconfiguration, are implemented using the analog circuit cell arrayaccording to the embodiment;

FIG. 21 is a diagram illustrating an example of layout at the firstmetal interconnect level in which the N-type transistor pair in theoperational amplifier of FIG. 17, arranged in a common centroidconfiguration, are implemented using the analog circuit cell arrayaccording to the embodiment;

FIG. 22 is a diagram explaining interconnect channels in the analogcircuit cell array according to the embodiment;

FIG. 23 is a diagram illustrating a modified example of the PMOS basiccell structure of the analog circuit cell array according to theembodiment;

FIG. 24 is a diagram illustrating a modified example of the PMOS basiccell structure of the analog circuit cell array according to theembodiment;

FIG. 25 is a diagram explaining interconnect channels at a third layerin the analog circuit cell array according to the embodiment;

FIG. 26 is a diagram explaining interconnect channels at the third layerin the analog circuit cell array according to the embodiment;

FIG. 27 is a diagram explaining interconnect channels at a fourth layerin the analog circuit cell array according to the embodiment;

FIG. 28 is a diagram illustrating an example of a bias circuitimplemented using the analog circuit cell array according to theembodiment;

FIG. 29 is a diagram illustrating an example of layout of the PMOSsection of the bias circuit up to the second interconnect level; and

FIG. 30 is a diagram illustrating an example of layout of the PMOSsection of the bias circuit at the first interconnect level.

DESCRIPTION OF EMBODIMENTS

As described previously, it had been difficult to increase the level ofintegration of analog circuits, and the lead time for production is alsolong.

Preferred embodiments will be explained with reference to accompanyingdrawings. The embodiment disclosed herein achieves an analog circuitthat has a high level of integration and that can be produced with ashort lead time.

FIG. 3 is a diagram illustrating the basic configuration of an analogcircuit cell array according to an embodiment. As illustrated in FIG. 3,the analog circuit cell array of the embodiment disclosed hereincomprises a PMOS array ARYP1 including PMOS basic cells PMOSC2 sarranged in 4 rows and 12 columns, and an NMOS array ARYN1 includingNMOS basic cells NMOSC2 s arranged in 4 rows and 12 columns. Asemiconductor device incorporating this analog circuit cell arrayfurther includes input signal terminals, output signal terminals, powersupply terminals, etc. plus the circuitry necessary for operating theanalog circuit cell array, but these are not illustrated here. Asemiconductor device having an analog/digital hybrid circuit can also beimplemented by mounting the analog circuit cell array of FIG. 3 in adigital circuit section such as a gate array. A desired analog circuitis achieved by forming interconnection patterns on the 48 PMOS basiccells PMOSC2 s and 48 NMOS basic cells NMOSC2 s.

As illustrated in FIG. 3, the PMOS array ARYP1 and NMOS array ARYN1 eachhave four basic cell rows. It is desirable that transistors, such as apair of transistors forming a differential pair or the like, for whichthe difference in characteristics needs to be minimized, be implementedusing basic cells in the second and third rows. That is, transistors,etc., that require high accuracy are formed using basic cells other thanthose adjacent to the edges of the PMOS array ARYP1 or NMOS array ARYN1.On the other hand, devices, such as antenna diodes to be describedlater, that can tolerate relatively large errors in theircharacteristics can be implemented using the basic cells in the firstand fourth rows without causing the problem of accuracy degradation.

If high-accuracy transistors, etc. are to be formed using basic cellsother than those adjacent to the edges of the PMOS array ARYP1 or NMOSarray ARYN1, and these transistors, etc. are to be arranged in a commoncentroid configuration, the PMOS array ARYP1 and NMOS array ARYN1 areeach required to have four rows and four columns at minimum. However,the number of rows and the number of columns may be increases; forexample, a six-row, six-column configuration may be used for each of thePMOS array ARYP1 and NMOS array ARYN1. A simple analog circuit can beachieved using a smaller number of basic cells, but a complex analogcircuit requires the use of a large number of basic cells. It istherefore desirable that a plurality of kinds of analog circuit cellarrays having different array configurations be made available for use,with provisions made to be able to select suitable ones according to theanalog circuit to be achieved.

FIG. 4 is a diagram illustrating an arrangement of 4×4 PMOS basic cellsPMOSC2 s in the PMOS array ARYP1 of FIG. 3. As illustrated in FIG. 4,each PMOS basic cell PMOSC2 has a P-type diffusion region PREG1 and twopolysilicon gate electrodes POLYG1 and POLYG2. Hereinafter, the PREG1 isrepresented by a rectangular pattern enclosed by solid lines, and eachPOLYG is indicated by oblique hatching. It should also be understoodthat unless otherwise specifically stated, the patterns on the samelayer are illustrated in the same way and any description once givenwill not be repeated thereafter. The portions of the P-type diffusionregion PREG1 that directly underlie the two polysilicon gate electrodesPOLYG1 and POLYG2 are first and second channel regions. The portion ofthe P-type diffusion region PREG1 that underlies the area between thetwo polysilicon gate electrodes POLYG1 and POLYG2 is a common drainregion. The portions of the P-type diffusion region PREG1 that underliethe area outside the two polysilicon gate electrodes POLYG1 and POLYG2are first and second source regions. In the illustrated example, eachPMOSC2 has an area bounded by double-dashed lines, and such PMOSC2 s arearranged in 4 rows and 12 columns, with a continuously formed N-typediffusion region NREG1 located between each row. The width of each ofthe first and second channel regions is chosen to provide a suitablechannel length or gate length, which is, for example, 2 μm. The width ofthe P-type diffusion region PREG1 defines the channel width or gatewidth, which is chosen to be, for example, 10 μm. The gate length andgate width are determined in accordance with the specification of theanalog circuit, ease of layout, etc. In the following description, thePOLYG1 and POLYG2 may sometimes be referred to collectively as POLYG.

FIG. 5 illustrates the condition in which a first metal interconnectlayer METAL1 is formed in the section including the PMOS basic cellsPMOSC2 s illustrated in FIG. 4. As will be described later, whenactually forming an analog circuit, the polysilicon gate electrodesPOLYGs and drain and source regions of each basic cell are connected tothe electrodes of the other basic cells, as well as to power supplyelectrodes, input terminals, output terminals, etc., via the first metalinterconnect layer METAL1. However, for simplicity of explanation, thediagram here illustrates the condition in which the connections betweenthe electrodes are not made.

In FIG. 5, the METAL1 is indicated by oblique cross-hatching, and eachCONT1 is represented by a square whose vertices are joined by diagonals.

As illustrated in FIG. 5, each PMOS basic cell PMOSC2 has four contactsGATE1, GATE2, GATE3, and GATE4 provided on the upper and lower endportions of the two polysilicon gate electrodes POLYG1 and POLYG2 thatextend outwardly of the P-type diffusion region PREG1, a drain electrodeDRAIN1 provided on the common drain region in the center, and sourceelectrodes SOURCE1 and SOURCE2 provided on the source regions on bothsides. The first metal interconnect layer METAL1 is provided on each ofthe N-type diffusion regions NREG1 s formed along the outer edges of thebasic cells in the first and fourth rows, respectively, and is connectedto the NREG1. The two polysilicon gate electrodes POLYG1 and POLYG2 andthe two source electrodes SOURCE1 and SOURCE2, respectively, arearranged symmetrically to each other with respect to the drain electrodeDRAIN1. Two PMOS transistors identical in size are thus formed in thePMOS basic cell PMOSC2. The four contacts GATE1, GATE2, GATE3, and GATE4are contact portions for connecting the gates of the two PMOStransistors to the METAL1. The DRAIN1 is the common drain electrode ofthe two PMOS transistors, and the SOURCE1 and SOURCE2 are the sourceelectrodes of the respective PMOS transistors.

In FIGS. 4 and 5, the PMOS basic cells PMOSC2 s are the basic units oflayout, and there is formed along the boundary between one row of basiccells and the next row of basic cells an N-type diffusion region NREG1that acts as a back gate electrode of the respective P-type transistors.

As will be described later, the two gate electrodes of each basic cellto be used are connected in common, and the two source electrodes arealso connected in common. This achieves in each basic cell the formationof a parallel connection of two transistors whose directions of currentare opposite to each other.

In the fabrication process of MOS transistors with ever decreasingfeature sizes, a step may be employed that implants ions from an obliquedirection. In this case, the width of the area where the highconcentration region of the source/drain diffusion layer overlaps thegate electrode can become different, for example, between the right andleft sides of the polysilicon gate electrode POLYG. This causes asituation where the effective parasitic resistance differs between theright and left sides of the POLYG. As a result, a situation occurs wherethe characteristics of the MOS transistor become different when thesource is formed in the diffusion layer on the right side of the POLYGand the drain in the diffusion layer on the left side than when thesource is formed in the diffusion layer on the left side of the POLYGand the drain in the diffusion layer on the right side. Because of suchcharacteristics of the fabrication process, the device geometry and themethod of using the device, including the direction in which the currentflows, must be made to match between the transistors that need matching.Matching the device characteristics, including the threshold voltage Vthand drain current, will hereinafter be referred to as matching.

However, the direction of current at the time of layout cannot bechecked by software called LVS or DRC that is used to check circuitinterconnections. The reason is that, in order to check the direction inwhich the current flows in the MOS transistor, a full understanding ofthe complex circuit becomes necessary which involves understanding thecircuit operation and recognizing the devices that need matching. As aresult, it has been the prior practice to manually check the sameness ofthe device arrangement, including the direction of current.

Accordingly, in such cases as where, when the source and drain of asingle MOS transistor are interchanged, the device characteristicschange and the effective parasitic resistance, for example, is differentbetween the source and drain, it is desirable to secure the symmetry byalso considering the direction of current.

In the layout of FIG. 5, by configuring the PMOS basic cell PMOSC2 intotwo PMOS transistors having the drain in common, two transistors whosedirections of current flowing from source to drain are opposite to eachother can be formed within the basic cell. As a result, when the basiccells are arranged, for example, in a common centroid configuration witheach basic cell as a unit, the total currents flowing in the transistorshaving different current directions are automatically added together,offering the effect that the mismatching between the MOS transistorshaving different current directions can be compensated for withouthaving to consider the direction of current in each basic cell.

Further, by constructing the PMOS basic cell PMOSC2 so as to include theN-type diffusion region NREG1 acting as the PMOS back gate electrode andalso include a substrate or well-feeding diffusion region in the basiccell structure, the need to separately provide a region for feedingN-type wells can be eliminated.

When the basic unit is configured as a parallel connection of twotransistors whose directions of current are opposite to each other, theadvantage of being able to eliminate the need to consider or examine thedirection of current in detail can be obtained, as long as the basiccell structure illustrated in FIG. 5 is observed. That is, thepossibility of overlooking the differences in characteristics due to thedifference in current direction can be reduced to zero.

If the offset current is to be minimized in an analog circuit, thecharacteristics of the transistors to be used must be made to match asmuch as possible. To avoid the effects of nonuniformity in resistexposure or etching, it has been general practice to use MOS transistorsof identical geometry and to place dummy devices around the devices thatneed accuracy. However, in recent MOS transistors with ever decreasingfeature sizes, a stress may be deliberately applied to the channelregion in order to increase the current driving capability, and fromthis fact, it can be seen that a change in mobility due to thedifference in stress induced by the device isolation region cannot beignored. Since trench-type isolation structures are often employed, theformation and arrangement of devices must be considered so that thefactors affecting the stress applied to the MOS transistor channelregion, such as the geometry of the isolation region, the geometry ofthe source/drain electrodes, and their ratio to the isolation region,become the same for all the devices.

Even in a structure in which PMOS transistors of identical geometry arearranged in a repeated fashion, an N-type well-feeding region inevitablybecomes necessary somewhere in the structure. The present inventors havediscovered that when the N-type well-feeding region is placed, forexample, in the outermost portion of the structure in which PMOStransistors are arranged in a repeated fashion, the well feeding regionitself disrupts the sameness of the isolation region. That is, it ispreferable to repeat the same geometry including the well-feedingregion, because then the symmetry and sameness of the transistorstructure, including the isolation region, can be ensured. There is thusa need to devise the basic transistor cell structure and interconnectstructure that can achieve such symmetry.

The layout of FIG. 5 achieves the structure in which the same geometry,including the well-feeding region, is repeated, while allowinginterconnects to be made to the devices. In the structure illustrated inFIG. 5, the PMOS basic cells PMOSC2 s are arranged in a repeatedfashion, including the N-type well-feeding regions NREG1 s. That is, thebasic cells PMOSC2 s such as the one bounded by the double-dashed linesare repeated in vertical and horizontal directions, and the NREG1 isshared between the upper and lower cells. This is illustrated by thefact that the double-dashed lines defining the upper and lower bounds ofthe PMOS basic cell PMOSC2 are drawn along the centerlines of therespective N-type well-feeding regions NREG1 s. This cell structure(basic structure) ensures the symmetry and sameness of the transistorstructure, including the isolation region, and offers the effect ofminimizing the difference in the stress applied to the channel region.This serves to further increase the degree of matching in mobility.

Further, by providing the four contacts GATE1, GATE2, GATE3, and GATE4in advance in such a manner that each contact can be connected to theMETAL1 independently of the others, it becomes possible to feed power tothe gates from any direction, while also achieving the effect ofenhancing the orderliness of the gate interconnect regions.

As described earlier, the two gate electrodes of each basic cell to beused are connected together. Therefore, the two polysilicon gateelectrodes POLYGs of each basic cell illustrated in FIG. 4 may be formedconnected together. FIG. 6 illustrates the condition in which the firstmetal interconnect layer METAL1 is formed on the basic cell polysilicongate electrodes POLYGs formed connected together.

The structure illustrated in FIG. 5 in which the two transistors haveindependent gates leaves room for the possibility that when there is noneed to care about the direction of current flow as in powerdowndevices, for example, the transistors can be used as two independenttransistors by interchanging the source and drain electrodes. However,in view of the basic constitution of connecting the two transistors ofdifferent currents in parallel within each basic cell, the two gates maybe connected directly by a POLYG interconnect line within the basiccell, as illustrated in FIG. 6. Considering the fact that it isdesirable to arrange the interconnect lines as symmetrically as possibleand the possibility that the circuit can be changed by changing only theinterconnect lines, four contacts should be provided for connecting thePOLYGs to the METAL1; since potentials can be supplied and coupled tothe gates within each basic cell by just making connections to the fourgate/METAL1 connecting portions, this achieves the effect of increasingdesign freedom in bringing out the signal interconnect lines.

Interconnects in the analog circuit cell array according to theembodiment will be described below.

It is known that the threshold voltage Vth of a MOS transistor changeswhen an interconnect line is present above the channel of the transistorthan when it is not. Broken bonds called dangling bonds exist at theinterface between the channel and gate oxide film of the MOS transistor,because the crystal structure abruptly changes across the interface.Since the dangling bonds act as carrier traps, it is desirable toterminate the dangling bonds with hydrogen. If a metal interconnect lineis present directly above the channel, it may prevent hydrogen fromreaching the channel interface in the annealing step which works toterminate the dangling bonds with hydrogen at the end of the fabricationprocess. It is therefore desirable that no interconnect lines beprovided on MOS transistors that need matching. Otherwise, between thetransistors that need matching, the entire structure including theinterconnect line above the channel of the MOS transistor must be formedin the same geometry.

To prevent the threshold voltage Vth of the transistor from changing, itis required in the layout of FIG. 5 that no interconnect lines beprovided above the regions where the two polysilicon gates POLYGsoverlap the P-type diffusion region PREG1, that is, above the channelregions in each of which an inversion layer in the transistor is formed.

FIGS. 7A and 7B are diagrams illustrating an example of howinterconnects are formed in the PMOS basic cell PMOSC2. FIG. 7Aillustrates the condition in which the first metal interconnect layerMETAL1 is formed, and FIG. 7B illustrates the condition in which asecond metal interconnect layer METAL2 is formed. As illustrated inparts (A) and (B) of FIG. 7, the PMOS basic cell PMOSC2 includes atleast three interconnect channels formed on the first metal interconnectlayer METAL1 in the lateral direction (current path direction). That is,it includes two lateral METAL1 interconnect channels within the basiccell structure and one lateral METAL1 interconnect channel which isshared with an adjacent basic cell (since it is shared, 0.5+0.5=1). Insome cases, five lateral METAL1 interconnect channels may be providedwithin the basic cell structure. Anyway, no interconnect lines areprovided above the current channels of the PMOS transistors.

Further, the PMOS basic cell PMOSC2 includes at least four interconnectchannels formed on the second metal interconnect layer METAL2 in thelongitudinal direction (gate width direction). That is, it includesthree longitudinal METAL2 interconnect channels within the basic cellstructure and one longitudinal METAL2 interconnect channel which isshared with an adjacent basic cell. The three longitudinal METAL2interconnect channels within the basic cell structure are provided abovethe drain electrode and source electrodes (METAL1) of the basic cellPMOSC2. In some cases, six METAL2 interconnect channels may be providedwithin the basic cell structure. The region underneath the longitudinalMETAL2 interconnect channel shared with the adjacent basic cell can alsobe used for the formation of a longitudinal METAL1 interconnect line.

By providing two lateral METAL1 interconnect channels formed on thefirst metal interconnect layer METAL1 in the lateral direction (currentpath direction) within the basic cell structure and one lateral METAL1interconnect channel shared with the adjacent basic cell, as describedabove, two lateral signal interconnect lines can be formed in additionto the interconnect line for well-feeding.

Furthermore, since the basic cell structure comprises a common drain andtwo independent source electrodes, five nodes, i.e., the two sources,the drain, the gate, and the well, must be connected using METAL1interconnects. To achieve this, an interconnect channel other than theMETAL1 at the gate/POLY contacts becomes necessary. To maintain thesymmetry of the cell structure, an even number of METAL1 interconnectchannels must be provided in addition to the METAL1 interconnect channelshared with the adjacent cell.

Further, by providing the METAL1 interconnect channels avoiding theportions above the current channels through which the current of the MOStransistor flows (the portions where the POLYGs overlap the PREG1), itis possible to achieve the structure in which no metal interconnectlines are provided above the gate channels; this prevents Vth fromchanging due to the presence of the metal interconnect line, and servesto enhance the relative accuracy.

Likewise, by providing the METAL2 interconnect channels above the drainelectrode and source electrodes (METAL1) of the basic cell PMOSC2, thatis, by providing the interconnect channels on the second metalinterconnect layer METAL2 in the longitudinal direction (gate widthdirection), i.e., three longitudinal METAL2 interconnect channels withinthe basic cell structure and one longitudinal METAL2 interconnectchannel shared with an adjacent basic cell, it is possible to secureregions where the four longitudinal signal interconnect lines can beformed.

By providing the METAL2 interconnect channels avoiding the portionsabove the current channels through which the current of the MOStransistor flows (the portions where the POLYG overlap the PREG1), it ispossible to achieve the structure in which no metal interconnect linesare provided above the current channels; this prevents Vth from changingdue to the presence of the metal interconnect line, and serves toenhance the relative accuracy. Then, by providing the METAL2interconnect channels above the drain electrode and source electrodes ofMETAL1 so as to avoid the portions above the current channels throughwhich the current of the MOS transistor flows, and providing the channelshared with the adjacent cell, the symmetry of the cell structure can bemaintained.

FIG. 8 is a diagram explaining the basic constitution of theinterconnect channels in the layout of the embodiment; here, thelongitudinally extending interconnect lines and the laterally extendinginterconnect lines are illustrated as being the interconnect lines thatcan be formed irrespective of the circuit connections.

Since no interconnect lines are allowed to be formed above the currentchannel regions of the PMOS transistors, the METAL2 interconnect linesextend in the longitudinal direction. Four interconnect lines, i.e., theinter-cell longitudinal interconnect line shared between adjacent PMOSbasic cells PMOSC2 s and the interconnect lines formed above the sourceand drain electrodes, are the longitudinal METAL2 interconnect linesthat can be provided in each column. As for the lateral METAL1interconnect lines, the interconnect line on the NREG1 and the lateralinterconnect lines in the gap between the NREG1 and the gate contactregion are the lateral METAL1 interconnect lines that can be formed.That is, in the illustrated structure, three lateral METAL1 interconnectlines can be provided in each basic cell row. The interconnect channelon the NREG1 is shared between the longitudinally adjacent cells.

From the standpoint of feeding VDD to the NREG1, it is desirable inprinciple that the NREG1 interconnect line be formed as a VDDinterconnect line, but if necessary, it is used not as a VDD but as asignal interconnect line in a specific region. Taking advantage of thefact that VDD need not necessarily be fed from the METAL1 in all theregions of the NREG1, the METAL1 interconnect line in a given region onthe NREG1 can be used as a signal interconnect line. Further, in thecase of the P-type basic cell, the interconnect line on the NREG1 is aVDD interconnect line as a general rule, but if necessary, it can beused locally as a signal interconnect line. The METAL1 interconnectlines illustrated extending longitudinally along the right and leftedges of the basic cell indicate that the regions directly beneath thelongitudinal METAL2 interconnect lines can also be used as METAL1interconnect regions. Or, the cell structure is designed so that theright and left boundaries of the cell can be used as longitudinal METAL1interconnect regions. When the cell structure is employed that allowsthe METAL1 interconnect lines to pass through the cell boundary regionsso that signals can be passed in the longitudinal direction, there isoffered the effect that the antenna diode can be connected as will bedescribed later.

While the configuration of the section including 4×4 PMOS basic cellsPMOSC2 s in the PMOS array ARYP1 has been described above, it will beappreciated that the configuration is the same for the correspondingsection including 4×4 NMOS basic cells NMOSC2 s in the NMOS array ARYN1,except that the polarity of the diffusion layer is inverted, andtherefore, a diagrammatic illustration and description thereof will notbe given herein.

Next, a description will be given of an embodiment for forming a bandgapcircuit of a series regulator by using the analog circuit cell array ofthe embodiment described above.

A microcomputer (MCU) is used as a programmable component in anelectronic apparatus. With advances in semiconductor processingtechnology, i.e. miniaturization technology, the range of applicationsof MCUs has been increasing at a rapid pace. The reason is that, withadvances in miniaturization technology, the processing capabilities ofthe MCUs have been improving and the cost per function has beendecreasing. As device geometries decrease, the voltage withstandingcapabilities of microstructure transistors forming digital circuits havebeen decreasing. For example, supply voltage for a CMOS circuit with agate length of 0.18 μm is generally on the order of 1.8 V. On the otherhand, in automotive applications, for example, it is often the case thatthe interface voltage to the MCU is required to satisfy the traditional5-V specification. There are also cases where the supply voltage orinterface voltage supplied from outside the MCU is required to be 5 V,while on the other hand, 1.8 V needs to be used as the supply voltage todigital circuitry due to the voltage withstanding capabilities of theinternal circuitry. In such cases, to reduce the number of externalcomponents it is standard practice to equip the MCU with a seriesregulator which generates 1.8-V power from the externally supplied 5-Vpower and supplies the 1.8-V power to the internal digital circuitry.

FIG. 9 is a diagram illustrating one example of the series regulatorcircuit, illustrating a typical configuration of a series regulatorwhich generates 1.8-V power from the externally supplied 5-V power. Theseries regulator includes a bandgap circuit BRG1 for generating areference voltage, an error amplifier EAMP1, an output transistor PMP1,and a resistive voltage-dividing circuit for dividing the regulatoroutput voltage. The resistive voltage-dividing circuit includesresistors RF1 and RF2 between which the regulator output voltage isdivided. In FIG. 9, Vbgr represents the reference voltage that thebandgap circuit BRG1 outputs, while EAMPO1 designates the output of theerror amplifier EAMP1, VOUT the regulator output, DIVO1 the output ofthe resistive voltage-dividing circuit, VDD the 5-V power supplied, forexample, from the outside, and GND the ground potential (0 V). In thefollowing description, the device name beginning with R indicates aresistor, and the device name beginning with PM indicates a PMOStransistor.

In the regulator circuit of FIG. 9, the bandgap circuit BRG1 generatesthe bandgap voltage Vbgr (1.2 V), i.e., the reference voltage that doesnot depend on temperature or supply voltage. The resistivevoltage-dividing circuit of RF1 and RF2 generates a divided voltage bydividing the regulator output voltage VOUT, for example, at ⅔. With theerror amplifier EAMP1 controlling the gate of the output transistorPMP1, negative feedback control is performed so that the output of theresistive voltage-dividing circuit, DIVO1, becomes identical with thereference voltage (bandgap voltage) Vbgr (1.2 V).

Since the voltage DIVO1, which is equal to the regulator outputmultiplied by ⅔, is identical with the bandgap voltage Vbgr (1.2 V), theregulator output voltage VOUT, for example, is controlled to theconstant voltage of 1.8 V (ideally) despite variations in temperature,supply voltage, and load current.

Ideally, the bandgap voltage is about 1.2 V and is independent oftemperature and supply voltage, but in practice, its output voltagechanges from circuit to circuit due to such factors as variations in theMOS transistor used to form the CMOS bandgap circuit. In a typical CMOSbandgap circuit, the output voltage varies within a range of ±8% of 1.2V.

If the reference voltage Vbgr is, for example, 1.2 V±8%, then in theabove example the regulator output voltage VOUT is also 1.2 V±8%(disregarding the offset voltage of the error amplifier), which is 1.2V±140 mV if the variation range is expressed in terms of absolute value.This means that the regulator output voltage VOUT fluctuates within arange of 1.66 V to 1.94 V around 1.8 V.

Since the regulator output voltage VOUT provides a supply voltage to alogic circuit formed from a CMOS circuit with a gate length of 0.18 μm,it follows that in one sample, the supply voltage to the MCU logiccircuit may be 1.66 V, while in another sample, the supply voltage tothe MCU logic circuit may be 1.94 V.

If the supply voltage to the MCU logic circuit is low, the delay time ofthe basic circuit forming the logic circuit increases, which isdisadvantageous from the viewpoint of operating frequency. On the otherhand, it is desired to hold the upper limit of the supply voltage to theMCU logic circuit, for example, within 2.0 V from the standpoint ofdevice reliability (for example, TDDB (Time-Dependent DielectricBreakdown), hot carrier degradation, etc.).

If the error of the regulator output voltage is large, it becomesdifficult to satisfy the upper limit of the supply voltage determinedfrom the standpoint of reliability, while at the same time satisfyingthe lower limit of the supply voltage that the regulator outputs andthat is determined by the operating speed requirement.

In view of the above situation, it is required, for example, in theregulator circuit that the output voltage accuracy of the bandgapcircuit be improved as much as possible.

FIG. 10 illustrates one example of the bandgap circuit. In an analogintegrated circuit, a reference voltage circuit called a bandgap circuitis widely used when a reference voltage independent of temperature andsupply voltage is needed. Since it can be easily combined with a digitalcircuit, the bandgap circuit is also widely used as a stable referencevoltage circuit in many important CMOS analog integrated circuits.

Various kinds of circuits that obtain a temperature-independentreference voltage by adding a forward biased pn junction voltage to avoltage proportional to absolute temperature (T) (generally calledPTAT—Proportional To Absolute Temperature) have been devised andcommercially implemented as bandgap circuits. It is known that theforward biased pn junction voltage (if approximated by a linearequation, or in the range where it can be approximated by a linearequation) is CTAT (Complementary To Absolute Temperature, that is,negatively linearly dependent on absolute temperature). It is known thatby adding a (suitable) PTAT voltage to this forward biased pn junctionvoltage, a reference voltage virtually independent of temperature can beobtained.

FIG. 10 illustrates a typical circuit example of such a bandgap circuit.In FIG. 10, Q1 and Q2 are pnp bipolar transistors (hereinafterabbreviated pnp BJTs), R1, R2, and R3 are resistors (their values arealso designated by R1, R2, and R3), AMP1 is an operational amplifiercircuit, GND is a GND terminal, Vbgr is the output reference voltage,and NODE1, IM, and IP are internal nodes. The values illustratedalongside the resistors are examples of the resistance values, and thenumber affixed to each BJT indicates the relative area ratio of the BJT.

The operation of the bandgap circuit of FIG. 10 will be explainedbriefly. It is known that, denoting the base-emitter voltage of the BJTor the pn junction forward bias voltage by Vbe, the relationship betweenthe pn junction forward bias voltage and absolute temperature is roughlygiven by the following equation (1).

Vbe=Veg−aT   (1)

(Vbe: pn junction forward bias voltage, Veg: silicon bandgap voltagewhich is about 1.2 V, a: temperature dependence of Vbe which is about 2mV/° C., T: absolute temperature) (The value of a varies depending onthe bias current, but it is known to be about 2 mV/° C. in the operatingrange.)

It is also known that the relationship between the emitter current IE ofthe BJT and the voltage Vbe is roughly given by the following equation(2).

IE=IOexp(qVbe/kT)   (2)

(IE: emitter current of BJT or diode current, IO: constant (proportionalto area), q: electron charge, k: Boltzmann constant)

By the negative feedback action of the operational amplifier AMP1, whenthe voltage gain of the AMP1 is sufficiently large, the voltages at theinputs IM and IP to the AMP1 become substantially identical with eachother and the circuit stabilizes. In this case, if the ratio of R1 to R2is, for example, chosen to be 1:10 (100 k:1 M) as illustrated in FIG.10, then the ratio of the magnitude of the current flowing through Q1 tothat through Q2 is 10:1, hence the current flowing through Q1 isdesignated by 10I and that through Q2 by I. (1×10 and I illustratedbelow Q1 and Q2 indicate the relationship between these currents.)

If the emitter area of Q2 is 10 times the emitter area of Q1 (×1 and ×10affixed to Q1 and Q2 in FIG. 10 indicate the relationship between theseemitter areas), and the base-emitter voltage of Q1 is denoted by Vbe1and the base-emitter voltage of Q2 by Vbe2, then from the equation (2)it can be seen that the relations expressed the following equations (3)and (4) hold.

10×I=IOexp(qVbe1/kT)   (3)

I=10×exp(qVbe2/kT)   (4)

Dividing both sides of (3) by both sides of (4) and denoting Vbe1-Vbe2as ΔVbe, the following equations (5) and (6) are obtained.

100=exp(qVbe1/kT−qVbe2/kT)   (5)

ΔVbe=(kT/q)ln(100)   (6)

That is, the difference ΔVbe between the base-emitter voltages of Q1 andQ2 is expressed by the logarithm (ln(100)) of the Q1/Q2 current densityratio 100 and the thermal voltage (kT/q). Since this ΔVbe is equal tothe potential difference across the resistor R3, the current of ΔVbe/R3flows through the resistors R2 and R3.

Therefore, the potential difference VR2 across the resistor R2 isexpressed by the following equation (7).

VR2=ΔVbeR2/R3   (7)

Since the voltage at IP and the voltage at IM are both equal to Vbe1,the reference voltage Vbgr is expressed by the following equation (8).

Vbgr=Vbe1+ΔVbeR2/R3   (8)

The pn junction forward bias voltage Vbe1 has negative temperaturedependence and decreases with increasing temperature (equation (1):Vbe=Veg−Ta), while on the other hand, ΔVbe increases with increasingtemperature as illustrated by the equation (6). By suitably selectingthe constant, the circuit can be designed so that the value of thereference voltage Vbgr becomes temperature independent. The value ofVbgr in that case is about 1.2 V (1200 mV) which corresponds to thesilicon bandgap voltage.

In this way, by suitably selecting the circuit constant in the circuitof FIG. 10, the temperature independent bandgap voltage can be generatedusing relatively simple circuitry.

While the circuit of FIG. 10 has the advantage that the referencevoltage can be generated using relatively simple circuitry as describedabove, it also has a shortcoming as will be described below.

FIG. 11 illustrates the problem associated with the circuit of FIG. 10.

In FIGS. 11, Q1 and Q2 are pnp bipolar transistors (hereinafterabbreviated pnp BJTs), R1, R2, and R3 are resistors (their values arealso designated by R1, R2, and R3), IAMP1 is an ideal operationalamplifier circuit, GND is a GND terminal, Vbgr is the output referencevoltage, NODE1, IM, and IP are internal nodes, VOFF is an equivalentvoltage source which represents the offset voltage of the operationalamplifier, and IIM is a negative input terminal of the ideal operationalamplifier IAMP1. The values illustrated alongside the resistors areexamples of the resistance values, and the number affixed to each BJTindicates the relative area ratio of the BJT.

To explain the problem associated with the circuit of FIG. 10, the AMP1in FIG. 10 is illustrated in FIG. 11 by the ideal operational amplifierIAMP1 and the equivalent offset voltage VOFF. Since the basic operationhas already been described with reference to FIG. 10, a description willbe given below of how the offset voltage VOFF affects the output voltageVbgr.

In a CMOS circuit, when forming a bandgap circuit, especially one suchas illustrated in FIG. 10, the effect of the operational amplifieroffset voltage is unavoidable. Ideally, when the input voltages IM andIP to the AMP1 of FIG. 10 are identical, the AMP1 produces an outputvoltage substantially equal to (for example) one half of the supplyvoltage. However, in a practical integrated circuit, since thecharacteristics of the devices forming amplifiers are not perfectlyidentical, the input voltages with which the output voltage of the AMP1becomes substantially equal to (for example) one half of the supplyvoltage differ for each individual amplifier, and the difference betweenthe input voltages at that time is called the offset voltage. It isknown that a typical offset voltage is about ±10 mV.

To explain how the characteristics of the practical amplifier affect theoutput voltage of the bandgap circuit, the AMP1 in FIG. 10 isillustrated in FIG. 11 by the ideal operational amplifier IAMP1 and theequivalent offset voltage VOFF. Here, the offset voltage of the idealoperational amplifier IAMP1 is 0 mV.

In the ideal circuit of FIG. 10, the voltages IM and IP are identical.On the other hand, in the practical circuit, since the input voltagesIIM and IP to the virtual ideal operational amplifier are identical, thevoltages IM and IP differ by an amount equal to the offset voltage VOFF.For simplicity, the potential difference that would occur under an idealcondition across the resistor R3 is expressed by the following equation(9).

VR3=ΔVbe   (9)

The potential difference VR3′ across the resistor R3 in FIG. 11 isexpressed by the following rough equation (9′). (It is to be understoodthat VOFF indicates the value of the offset voltage VOFF.)

VR3′=ΔVbe+VOFF   (9′)

The potential difference VR2′ across the resistor R2 is expressed by thefollowing equation (10).

VR2′=(ΔVbe+VOFF)R2/R3   (10)

Hence, Vbgr is expressed by the following equation (11).

Vbgr=Vbe1+VOFF+(ΔVbe+VOFF)R2/R3   (11)

If it is assumed that R2/R3=5 as illustrated in FIG. 3, the value ofVbgr is equal to the sum of the ideal value and the offset valuemultiplied by (about) 6.

In the circuit examples illustrated in FIGS. 10 and 11, in order tominimize the effect of the offset voltage of the operational amplifier,the area of Q2 is set to be 10 times that of Q1 and the current flowingthrough Q1 is set to be 10 times the current flowing through Q2.Accordingly, the potential difference across R3, for example, is givenby the following equation (12).

ΔVbe=(kT/q)ln(100)=26 mV×4.6=120 mV   (12)

As illustrated by the equation (12), the potential difference can bemade relatively large at 120 mV. The effect of VOFF can be heldrelatively low in this way but, even in this case, if the bandgapvoltage of 1200 mV is to be obtained by adding the PTAT voltage to theVbe of about 600 mV, the value of the equation (12) must be multipliedby 5 and added to Vbe1. As a result, if the offset voltage VOFF exists,the effect of VOFF on Vbgr is multiplied by about (1+5)=6. (The BGRoutput equation illustrated in FIG. 11 indicates this effect of theoffset voltage.)

That is, while the circuit of FIG. 10 has the advantage that the bandgapcircuit can be achieved with relatively simple circuitry, it has thelimitation that the accuracy of the reference voltage Vbgr that can beachieved is limited by the offset voltage of the operational amplifier.

The above description has been given by taking the circuit of FIG. 10 asan example to explain that the offset voltage of the operationalamplifier used in the BGR circuit must be minimized in order to improvethe accuracy of the output voltage of the bandgap circuit. As earlierdescribed, a layout strategy called common centroid has been known inthe prior art for minimizing the offset voltage.

FIG. 12 illustrates the operational amplifier at the transistor level.

In FIG. 12, PMAC1, PMAC2, and PMAC3 are PMOS transistors forming acurrent mirror, PMAD1 and PMAD2 are PMOS transistors forming adifferential pair, RB1 is a bias resistor, NMAL1 and NMAL2 are NMOStransistors forming loads for the differential pair, NAMD1 is an NMOStransistor forming an amplifier stage whose source is grounded, CC1 is aphase compensation capacitor, IMOP1 is a negative input terminal of theoperational amplifier, IPOP1 is a positive input terminal of theoperational amplifier, NDD1 and NDD2 are drain nodes of the differentialpair, NDS1 is a common source node of the differential pair, GND is aGND potential (0 V), and OUTOP1 is the output of the operationalamplifier.

The circuit illustrated in FIG. 12 is a commonly used operationalamplifier, and its operation will not be described in detail here.

It is known that the devices that need matching to minimize the inputreferred offset of the operational amplifier circuit of FIG. 12 are,first of all, the PMOS transistors PMAD1 and PMAD2. It is also requiredthat the device characteristics of the NMOS transistors NMAL1 and NMAL2be identical. A common centroid layout has been known as a layout schemethat achieves optimum arrangement of such transistors or devices thatneed matching.

A layout example in which the PMOS transistors PMAD1 and PMAD2 in FIG.12 are arranged in a common centroid configuration has been given in thepreviously illustrated FIG. 2. Since the common centroid layout hasalready been explained with reference to FIG. 2, the explanation willnot be repeated here.

The foregoing description has illustrated that the output voltage of thebandgap circuit has a bearing on the output voltage accuracy of theregulator circuit, that the output voltage accuracy of the bandgapcircuit is important, that the offset voltage of the operationalamplifier must be reduced in order to maximize the accuracy of thebandgap voltage, and that the common centroid layout is known as ascheme for achieving that purpose.

It is known that the offset voltage of the operational amplifier anddigital circuits are affected by the antenna effect. The antenna effectrefers to a phenomenon in which, during a process (fabrication process)using a plasma for the fabrication of a MOS transistor, an electricalstress is applied to the gate oxide film of the MOS transistor becauseof the presence of electric charges in the plasma, leading to areliability problem or causing the characteristics of the MOS transistorto change. When processing the metal interconnect line connected to thegate oxide film, the metal interconnect line being processed acts as anantenna and gathers electric charges, which can damage the gate oxidefilm; therefore, this phenomenon is generally called the antenna effect.

It has long been pointed out that, due to the electric charges gatheredby the antenna (the metal interconnect line connected to the gate)during the processing of the metal interconnect line in the plasmaprocess, the threshold voltage Vth of the MOS transistor changes, andunevenness in the antenna effect causes the offset voltage of thedifferential circuit to increase.

FIGS. 13A and 13B are diagrams explaining the antenna effect. In FIGS.13A and 13B, PML1 and PML2 are PMOS transistors, NML1 and NML2 are NMOStransistors, VDD is a terminal which becomes a positive power supplyterminal after the formation of the circuit, GND is a terminal whichbecomes a GND terminal after the formation of the circuit, METAL1 is ametal interconnect line on the first layer, METAL2 is a metalinterconnect line on the second layer, VIA1 is a plated-through hole,and IPLSM is the current that flows in the plasma process.

The method of depicting the METAL1, METAL2, and VIA1 in FIGS. 13A and13B is the same as that used in FIGS. 2 and 12, and the descriptionthereof will not be repeated here.

FIG. 13A illustrates the current IPLSM that flows during the etching(patterning) of the METAL2. In the interconnection pattern such asillustrated in FIG. 13A, since the METAL2 is connected through the VIA1to the METAL1 during the etching of the METAL2, the METAL2 is coupled tothe drain junction between the PML1 and NML1. Accordingly, the electriccharges gathered by the interconnect line during the etching of theMETAL2 is discharged, for example, through a discharge path by theleakage current of the drain junction between the PML1 and NML1.

On the other hand, FIG. 13B illustrates the current that flows duringthe etching of the METAL1 which precedes the etching of the METAL2.According to the interconnect structure such as illustrated in FIG. 13B,the METAL1 connected to the drain of the PML1 and NML1 and the METAL1connected to the drain of the PML2 and NML2 are formed as separateinterconnect lines during the etching of the METAL1. As a result, theelectric charged gathered by the METAL1 connected to the drain of thePML1 and NML1 are discharged through the same discharge path as thatillustrated in FIG. 13A (that is, the drain of the PML1 and NML1).However, there is no discharge path for the electric charges gathered bythe METAL1 connected to the gate of the PML2 and NML2 during the etchingof the METAL1. There is therefore no alternative for the chargesgathered during the plasma process but to flow into the gate oxide film,and the IPLSM flows as a tunneling current through the gate oxide film.This current causes the Vth of the MOS transistor to change or damagesthe gate oxide film.

To avoid such damage to the gate oxide film during the processing ofinterconnect lines, a protection diode called an antenna diode hastraditionally been used.

FIGS. 14A and 14B illustrate one example of the protection diode. FIGS.14A and 14B differ from FIGS. 13A and 13B by the inclusion of the diodeDIO1 and the modification of the METAL1 pattern for the connection ofthe diode DIO1, and the following description focuses on thesedifferences.

FIG. 14A, as in FIG. 13A, illustrates the current that flows during theprocessing of the METAL2. In FIG. 13A, the current does not flow intothe gate oxide film during the processing of the METAL2 because themetal being processed is coupled to the drain junction. In FIG. 14Aalso, since the interconnect structure is the same as that illustratedin FIG. 13A, the electric charges gathered by the interconnect line inthe plasma process during the processing of the METAL2 do not causedamage to the gate oxide film. In FIG. 13B, because of the presence ofthe METAL1 connected only to the gate oxide film during the processingof the METAL1, the electric charges gathered during the processing ofthe METAL1 flows into the gate oxide film, which can cause damage to thegate oxide film. To avoid such a situation, in the structure of FIGS.14A and 14B, the diode DIO1 called an antenna diode is connected to theMETAL1 interconnect line connected to the gate. The provision of such acurrent path DIO1 serves to prevent the current from flowing into thegate oxide film during the processing of the METAL1 connected to thegate. The electric charges gathered by the METAL1 are discharged, forexample, as the leakage current of the DIO1 through the IPLSM pathillustrated in FIG. 14B. The DIO1 acts as a current discharge pathduring the processing of the interconnect lines, but during normaloperation after the manufacture, this diode is reverse biased so that ithas hardly any effect on the operation, though it induces a small amountof leakage current and an increase in capacitance and area.

FIG. 15 illustrates one example of the plane structure of the antennadiode, and FIG. 16 illustrates its cross-sectional structure. The methodof depicting the POLYG, NREG1, PREG1, CONT1, METAL1, etc. in FIG. 15 arethe same as that used in FIG. 1, and any description once given will notbe repeated here. DIO1 in FIG. 15 indicates the portion that acts as theantenna diode. It is known that the gate oxide film can be protected byconnecting a diode with a very small area to the METAL1 connected to thegate electrode, as illustrated in FIG. 15. For example, by connecting anN-type diffusion region NREG1 in the P-type substrate to the metal(METAL1), the reversed biased diode can be connected to the interconnectline connected to the gate electrode.

In FIG. 16, PSUB is the P-type substrate, PREG1 is the P-type diffusionlayer (illustrated as the P+ region), NREG1 is the N-type diffusionlayer (illustrated as the N+ region), GND is the portion that acts asthe GND terminal, METAL1 is the interconnect line on the first layer,and METAL2 is the interconnect line on the second layer. As illustratedin FIG. 16, since the P-type substrate PSUB is held at GND potentialduring operation after the manufacture, the PSUB serves as the anode ofthe DIO1 and the NREG1 as the cathode. That is, as previously described,the diode is reverse biased so that it does not affect the circuitoperation.

As explained with reference to FIGS. 14 to 16, it has been known that byusing an antenna diode for the protection of the gate oxide film, it ispossible to prevent the degradation or breakage of a microstructuretransistor in a digital circuit or to prevent the increase of the offsetvoltage in the analog circuit section.

Based on the techniques described above, a bandgap circuit such asillustrated in FIG. 17 is fabricated here.

In FIG. 17, PMAC2 and PMAC3 are PMOS transistors forming a currentsource, PMAD1 and PMAD2 are PMOS transistors forming a differentialpair, R1, R2, and R3 are resistors, NMAL1 and NMAL2 are NMOS transistorsforming loads for the differential pair, NAMD1 is an NMOS transistorforming an amplifier stage whose source is grounded, CC1 is a phasecompensation capacitor, IM is a negative input to an operationalamplifier, IP is a positive input to the operational amplifier, NDD1 andNDD2 are drain nodes of the differential pair, NDS1 is a common sourcenode of the differential pair, VDD is, for example, a 5-V power supply,GND is a GND potential (0 V), Vbgr is the output of the bandgap circuit,Q1 and Q2 are pnp bipolar transistors (hereinafter abbreviated pnpBJTs), the number affixed to each BJT indicates the relative area ratioof the BJT, PMGD1 and PMGD2 are transistors acting as antenna diodes,and PB1 is a bias voltage. (The device name beginning with R indicates aresistor, the device name beginning with PM indicates a PMOS transistor,the device name beginning with NM indicates an NMOS transistor, and thedevice name beginning with C indicates a capacitor.)

In FIG. 17, the devices and nodes corresponding to those in FIGS. 10 and12 are indicated by the same designations so that their correspondencescan be easily identified.

As previously explained with reference to FIG. 12, the devices that needmatching to minimize the input referred offset of the operationalamplifier circuit are, first of all, the PMOS transistors PMAD1 andPMAD2. It is also required that the device characteristics of the NMOStransistors NMAL1 and NMAL2 be identical.

FIG. 18 is a diagram illustrating a layout example in which the two PMOStransistors PMAD1 and PMAD2 forming the PMOS transistor pair in thebandgap circuit of FIG. 17 and the two PMOS transistors PMGD1 and PMGD2acting as the antenna diodes are formed using an analog circuit cellarray. The layout example of FIG. 18 illustrates the interconnectionpattern at the METAL1 layer level.

In FIG. 18, CONT1 is a contact, PREG1 is a P-type diffusion region,METAL1 is an interconnect line on the first layer, POLYG is a Poly-Sigate electrode (polysilicon gate electrode), NREG1 is an N-typediffusion region, VDD is a region that acts as a positive power supply,PMAD1A and PMAD1B are transistors arranged by splitting the PMAD1illustrated in FIG. 17, PMAD2A and PMAD2B are transistors arranged bysplitting the PMAD2 illustrated in FIG. 17, and PMGD1 and PMGD2 are PMOStransistors acting as the antenna diodes.

PMAD1A and PMAD1B in FIG. 18 are transistors arranged by splitting thePMAD1 illustrated in FIG. 17, and PMAD2A and PMAD2B are transistorsarranged by splitting the PMAD2 illustrated in FIG. 17. The PMAD1A andPMAD1B and the PMAD2A and PMAD2B, respectively, are arranged diagonallyopposite each other to achieve a common centroid configuration.

Suppose, for example, that the oxide film thickness is formed unevenlyat the time of manufacture. The PMAD1 comprises a parallel connection ofthe PMAD1A formed at the left and PMAD1B formed at the right. On theother hand, the PMAD2 comprises a parallel connection of the PMAD2Bformed at the left and PMAD2A formed at the right; as a result, betweenthe PMAD1 and PMAD1, the difference in the device characteristicsbetween the left and the right is canceled out. It is also obvious thatthe difference in the device characteristics between the top and thebottom are canceled out in like manner.

As earlier described, in the fabrication process of MOS transistors withever decreasing feature sizes, a step may be employed that implants ionsfrom an oblique direction. In this case, the width of the area where thehigh concentration region of the source/drain diffusion layer overlapsthe gate electrode can become different, for example, between the rightand left sides of the Poly-Si gate electrode POLYG. This causes asituation where the effective parasitic resistance differs between theright and left sides of the POLYG, and as a result, a situation occurswhere the characteristics of the MOS transistor become different whenthe source is formed in the diffusion layer on the right side of thePOLYG and the drain in the diffusion layer on the left side than whenthe source is formed in the diffusion layer on the left side of thePOLYG and the drain in the diffusion layer on the right side. Because ofsuch characteristics of the fabrication process, the device geometry andthe method of using the device, including the direction in which thecurrent flows, must be made to match between the transistors that needmatching.

However, the direction of current at the time of layout cannot bechecked by software called LVS or DRC that is used to check circuitinterconnections. The reason is that, in order to check the direction inwhich the current flows in the MOS transistor, a full understanding ofthe complex circuit becomes necessary which involves understanding thecircuit operation and recognizing the devices that need matching. As aresult, it has been the prior practice to manually check the sameness ofthe device arrangement, including the direction of current. To solvethis problem, in the layout of FIG. 18, two MOS transistors having acommon drain, as illustrated in FIG. 18, are used as the basic layoutunit.

In FIG. 18, two PMOS transistors having a common drain and having thesame gate width and gate length are employed as the basic unit of thelayout. With the DRAIN1 in the center as the drain and the left andright electrodes as the sources, a parallel connection of twotransistors whose directions of current are opposite to each other isrealized within each basic cell unit. This offers the effect that whenarranging the PMAD1 and PMAD2 in a common centroid configuration, asillustrated in FIG. 18, there is no need to consider the direction ofcurrent of each individual transistor. The reason is that the PMAD1A,PMAD1B, PMAD2A, and PMAD2B are each formed from a parallel connection ofa transistor in which the current flows in the rightward direction and atransistor in which the current flows in the leftward direction and, asa result, the differences in device characteristics due to thedifference in current flow direction are canceled out.

When the basic unit is configured as a parallel connection of twotransistors whose directions of current are opposite to each other, theadvantage of being able to eliminate the need to consider or examine thedirection of current in detail can be obtained, as long as the basiccell structure illustrated in FIG. 18 is observed. That is, thepossibility of overlooking the differences in characteristics due to thedifference in current direction can be reduced to zero.

In FIG. 18, the peripheral area of the array of basic PMOS transistorcells PMOSC2 arranged in four rows and four columns functions similarlyto the prior art dummy device. That is, the center area where thetransistors are orderly arranged in a repeated fashion is less affectedby the peripheral area, and it is expected that processing uniformityimproves in this area; therefore, the devices that need matching areplaced in the center area.

For this reason, in FIG. 18 also, the PMAD1A, PMAD2A, PMAD1B, and PMAD2Bare arranged in the center of the array.

If, for example, the antenna diode for protecting the gate oxide film isprovided as a dedicated antenna diode outside the transistor array,there arises the problem that it is difficult to connect the diode withthe METAL1 interconnect line. On the other hand, if the diode ofdifferent geometry is added to the array of the orderly arrangedtransistors, the symmetry and sameness of the transistor geometry andisolation region geometry cannot be maintained. Furthermore, if thediode is placed, for example, within the PMOS basic cell, the problem ofthe sameness within the layout unit can be solved, but a large number ofdiodes that are not actually used have to be provided, which isdisadvantageous from the viewpoint of efficient utilization of chip realestate.

In view of the above, in the layout of the present embodiment, the drainelectrode of a basic cell transistor, for example, is used as an antennadiode. (Instead, the source electrode may be used.)

As illustrated in the circuit diagram of FIG. 17, for example, toprotect the gates of the PMOS transistors that need matching, the drainelectrodes of the PMOS transistors whose gates are held at the VDDpotential are connected to the gates of the PMAD1 and PMAD2 by usingMETAL1 interconnect lines. When the gates and sources of the PMGD1 andPMGD2 are held at VDD, the PMGD1 and PMGD2 are held in the OFF state anddo not function as transistors. By using the drain junctions of thePMGD1 and PMGD2 as the diodes, the gate oxide films can be protected bythe antenna diodes without disrupting the orderliness and sameness ofthe transistor array. As illustrated in FIG. 18, interconnect channelsare provided on the PMOS basic cells and along the left and right sidesof each PMOS basic cell so that the METAL1 interconnect lines can beadded. By employing such a basic cell structure, the gates of the PMOSbasic cells arranged in a common centroid configuration can be connectedtogether by the METAL1 interconnect lines for connection to the drainsof the respective transistors acting as the antenna diodes.

In this way, the transistors that need matching are placed in the centerarea of the PMOS array, and the antenna diodes are formed using edgeportions of the array. The characteristics of the antenna diodes neednot be identical. In the example illustrated in FIG. 18, the PMGD2 isplaced in the top row of the array, and the PMGD1 in the bottom row ofthe array. Since the PMAD1 and PMAD2 are placed in the second and thirdrows, interconnect lines for connecting the antenna diodes to the gatesto be protected need to be formed along the longitudinal direction usingMETAL1. That is, it is required that the transistor array be configuredto provide a structure that allows the use of the longitudinal METAL1interconnect lines. FIG. 18 illustrates one example of the structurethat satisfies this requirement.

Since an N region NREG1 for feeding an N-type well in PMOS is includedin the basic cell structure to maintain the uniformity and periodicityof the device isolation region, a well-feeding region exists betweeneach row of basic cells. There is no need to supply the VDD potential toall the NREG1 regions by using METAL1 but, in principle, it is desirablethat the NREG1 regions be supplied with VDD by using METAL1 (connectedvia the contacts CONT1 s). Further, since the gate POLYG region needsconnecting portions (GATE1, GATE2, GATE3, and GATE4 in FIG. 5) forconnecting to the POLYG-connecting METAL1, to construct the circuit aregion where an interconnect line can be formed in the lateral directionmust be secured somewhere other than directly above the NREG1.

In view of this, a region where a METAL1 interconnect line can be formedin the lateral direction is secured between the NREG1 and the gatecontact region in FIG. 18. The reason that METAL1 is used for theinterconnect line in this region is that it is preferable to use METAL2for longitudinal interconnect lines.

FIG. 19 is a diagram illustrating the layout of FIG. 18 with METAL2 sand VIA1 s added to it (some METAL1 s are also added). The diagramexplains how the nodes can be connected or brought outside in thestructure of FIG. 18. Examples of the connections will be described byalso referring to FIG. 18 for portions where the layers overlap eachother and appear confusing.

The explanation of the layout, including the METAL2 interconnect lines,will be continued with reference to FIG. 19. In FIG. 19, METAL2 is ametal interconnect line on the second layer, VIA1 is a plated-throughhole, and IM, IP, VDD, NDS1, NDD1, and NDD2 are the portionscorresponding to the circuit nodes having the same designations in FIG.18. In FIG. 19, PVIA1 is illustrated by a filled square, and METAL1 bycross hatching with oblique lines inclined at 45 degrees. METAL2 isindicated by hatching with horizontal and vertical lines crossing atright angles. The method of depicting the other layers is the same asthat used in the previously illustrated figures.

From FIG. 18, it can be seen that the drain of the PMGD2 can beconnected to the gates of the PMAD2A and PMAD2B by the METAL1. Likewise,it can be seen that the gates of the PMAD1A and PMAD1B can be connectedto the drain of the PMGD1 by the METAL1. FIG. 19 illustrates an exampleof how the connections are made to the sources and drains of the PMAD1and PMAD1 and the gates and sources of the PMGD1 and PMGD2.

The source electrodes of the PMAD1A, PMAD2A, PMAD2B, and PMAD1B must beconnected to the common source node NDS1. To achieve these connections,the sources of the PMOS transistors of the differential pair areconnected via the VIA1 s to the common node by using the METAL2interconnect lines extending longitudinally above the source electrodes.Since the source and drain of each transistor are invariably providedwith the contacts CONT1 s and the METAL1 s (as illustrated in FIG. 18)for connecting the diffusion layers to the interconnect lines, theinterconnect layer passing above these regions in the longitudinaldirection is naturally the METAL2 layer. As a result, the interconnectlines connecting between the two METAL2 interconnect lines connectingthe sources of the PMAD1A and PMAD2B and between the two METAL2interconnect lines connecting the sources of the PMAD2A and PMAD1B areMETAL1 interconnect lines or METAL3 interconnect lines on the thirdlayer.

In the example illustrated in FIG. 19, the METAL2 interconnect linesbrought out from these source electrodes are connected via the VIA1 s tothe laterally extending METAL1 interconnect line designated by NDS1.

As described with reference to FIG. 18, it is preferable to use METAL1interconnect lines as lateral interconnect lines and METAL2 interconnectlines as longitudinal interconnect lines; the reason is that a greaternumber of longitudinal interconnect lines can be secured when METAL2interconnect lines are used as longitudinal interconnect lines asillustrated in FIG. 19 than would be the case if METAL1 interconnectlines were used as longitudinal interconnect lines. Since

METAL1 interconnect lines are already formed in the source and drainregions, if METAL1 were to be used for the longitudinal interconnectlines, only the region between the transistor and its adjacenttransistor could be used for the interconnect lines. In contrast, whenMETAL2 interconnect lines are used as the longitudinal interconnectlines, the advantage is that that the regions above the drain and sourcecan be used as the longitudinal interconnect channels.

As already explained, the threshold voltage Vth of the MOS transistormay change when an interconnect line is present above the currentchannel of the transistor than when it is not. To avoid this,interconnect lines cannot be formed above the regions where the POLYGsoverlap the PREG1 in FIG. 19, i.e., above the channel regions in each ofwhich an inversion layer in the transistor is formed. In FIG. 19 also,no interconnect line whatsoever is provided above the current channel ofthe transistor. This also explains why it is advantageous to form theMETAL2 interconnect lines in the longitudinal direction and use theregions above the drain and sources as the interconnect channels.

The METAL1 interconnect line in the uppermost portion of the array isillustrated as being VDD. Since this portion is the portion for feedingthe N-type well region, the METAL1 in this portion is connected to VDD.Further, the well-feeding region between each row of the array, where aMETAL1 interconnect line can be formed, is also VDD. By connecting theseMETAL1 interconnect lines by the METAL2 in the longitudinal direction,VDD can be supplied to the various parts. This also achieves a mesh-likepower supply configuration, which is advantageous.

In FIG. 18, the gate and source of the PMGD2 are illustrated as notbeing connected to the VDD, but they can be connected to the VDDinterconnect line at the peripheral edge of the array by using thelongitudinally extending METAL2 and laterally extending METAL1interconnect lines as illustrated in FIG. 19. For the PMGD1 also, as canbe seen from FIG. 19, VDD can be fed to the gate and source in the samemanner as the PMGD2.

The NDD1 must be connected to the drains of the PMAD1A and PMAD1B. InFIG. 19, the NDD1 is illustrated as being a METAL2 interconnect line. Itcan be connected by using the VIA1 s and the laterally extending METAL1and longitudinally extending METAL2 interconnect lines. Though notillustrated in FIG. 18 to simplify the illustration, in FIG. 19 thedrain electrode of the PMAD2B is connected to the NND2 of METAL2 byusing a METAL1 interconnect line. By providing a gap capable of passinga METAL1 interconnect line between the gate/METAL1 connecting portionsof the basic cell, the connection such as illustrated in FIG. 19 becomespossible.

Since the transistor gate length L is as large as 1 μm to 2 μm in thecase of an analog circuit, it is sufficiently possible to pass a METAL1interconnect line through the gap between the METAL1 s of the GATE1 andGATE3 or the gap between the METAL1 s of the GATE2 and GATE4 of the PMOSbasic cell illustrated in FIG. 5.

Since the METAL2 interconnect line for connecting the drain of thePMAD1A passes above the drain of the PMAD2B, the drain of the PMAD2B isbrought out using METAL1. Likewise, the drain electrode of the PMAD2A isbrought out using the METAL1 interconnect line passing between themetals of the gate contact portions. This is because the METAL2interconnect line IM for bringing out the gates of the PMAD1A and PMAD1Bis passed above the drain electrode of the PMAD2A.

The METAL2 interconnect lines IM and IP extend in the longitudinaldirection and are connected to the gates of the PMAD1 and PMAD2,respectively. Since the gates of the PMAD1 and PMAD2 are protected bythe drains of the PMGD1 and PMGD2 acting as the antenna diodes, thegates can be brought out by connecting the METAL1 interconnect lines tothe METAL2 interconnect lines.

While FIG. 19 has only illustrated the differential pair, PMAD1 andPMAD2, and their connections to the antenna diodes, it will beappreciated that any desired circuit can be constructed using theconstitution of FIG. 19. That is, the common centroid layout can beachieved using the constitution of the basic cell structure andinterconnect channels such as those illustrated in FIGS. 18 and 19. Itwill also be appreciated that while the transistors not used areillustrated as being left unconnected, these transistors may also beused as circuit elements, that while the array has been illustrated asincluding four columns for convenience of illustration, the number ofcolumns may be suitably chosen, that while the number of rows has alsobeen illustrated as being four, this number is the minimum number ofrows required to allow the use of the center area of the array, and alarger number of rows may be used, and that when leaving the transistorsin the peripheral area unused, their gates, drains, sources, etc. can beeasily fixed to the power supply potential. The contacts and METAL1interconnect lines for the well-feeding regions are not fullyillustrated, but the VDD potential can be supplied as desired by forminginterconnect lines where necessary.

The above has described the example of implementing the PMOS transistorsPMAD1 and PMAD2 of the operational amplifier in the bandgap circuit ofFIG. 17 by using the PMOS array ARYP1. The NMOS transistors NMAL1 andNMAL2 of the operational amplifier can be implemented in like manner byusing the NMOS array ARYN1.

FIG. 20 illustrates an NMOS array layout/connection example for the NMOSarray ARYN1 up to the METAL2 interconnect level. FIG. 21 illustrates thelayout at the METAL1 level by removing the METAL2 regions. Referring tothese figures, an explanation will be given of how the NMOS circuitsection can also be constructed using the constitution of the inventionso far described by taking PMOS as an example.

If the offset voltage of the operational amplifier in the bandgapcircuit of FIG. 17 is to be minimized, it is required that thecharacteristics of the NMAL1 and NMAL2 be identical. It is alsodesirable that the characteristics of the NMAD1 be identical with thoseof the NMAL1 and NMAL2, but since this makes the illustrationcomplicated, the following describes a common centroid layout example ofthe NMAL1 and NMAL2 with reference to FIGS. 20 and 21.

The method of depicting the layout layers in FIGS. 20 and 21 is the sameas that used in the previously illustrated figures. The layout for theNMOS transistors illustrated here is essentially the same as that forthe PMOS array, except that the source and drain regions are formed fromNREG1 and that the well-feeding regions formed from NREG1 in the PMOSarray are replaced by P-substrate feeding regions PREG1 s.

In FIG. 20, NDD1 and NDD2 are interconnect lines corresponding to thecircuit nodes NDD1 and NDD2 of FIG. 17. The NMAL1 and NMAL2 are split,the former into NMAL1A and NMAL1B and the latter into NMAL2A and NMAL2B,and are arranged in a common centroid configuration. Since the gate anddrain of the NMAL1 are the same node, the METAL1 at the contact potionof the gate region and the METAL1 in the drain region are connectedtogether, as illustrated in FIG. 21.

As illustrated in FIG. 20, the METAL2 interconnect line NDD1, forexample, can be connected to the drain of the NMAL1A through VIA1 and tothe METAL1 in the gate region of the NMAL2B through VIA1, therebyaccomplishing the connections to the NDD1. Likewise, the NDD2 can beconnected to the NMAL2A by connecting the longitudinal METAL2interconnect line to the drain through VIA1. In the case of FIG. 20, theMETAL2 interconnect line of the NDD1, for example, passes above thedrain of the NMAL2B; therefore, the drain should be brought out using aMETAL1 interconnect line and connected to the NDD2. The GND interconnectline should be connected to the source electrodes by using the METAL1interconnect line for feeding the PREG1, and then using longitudinalMETAL2 interconnect lines.

As illustrated in FIGS. 20 and 21, in this case, since the NMOS sourcepotential is GND, the interconnections are simpler than those for thePMOS differential circuit section. In the PMOS differential circuitsection, interconnections become necessary for the NDS1 since the sourcepotential is not VDD, but in the case of the NMAL1 and NMAL2, the sourceof each NMOS transistor need only be held at the same potential as theP-substrate feeding region, which serves to reduce the total number ofinterconnect lines required. That is, if the layout can be accomplishedfor the circuit section in which the source potential is not the powersupply potential, as illustrated in FIG. 18, then any desired circuitsufficient for practical use can be connected and implemented using theconstitution of the present invention.

FIG. 22 is a diagram illustrating the interconnections when interconnectlines are arranged in a virtual fashion in the regions where theinterconnections can be made to the NMOS transistors, as in the case ofFIG. 8. It can be seen that the interconnections can be made to the NMOStransistors in the same manner as the PMOS transistors, except that thepolarity of the diffusion layer is inverted, and that in the case of theNMOS transistors also, the interconnect channels can be arranged byavoiding the regions above the current channels.

Next, an alternative example of the basic cell repeating structure willbe described with reference to FIGS. 23 to 28.

FIG. 23 illustrates the alternative example of the basic structure ofthe PMOS array. The method of depicting the layers is the same as thatused in FIG. 5. FIG. 5 has illustrated the structure in which the NREG1s for feeding the N-type wells are provided on the upper and lower sidesof the basic cells. In FIG. 23, on the other hand, the structure is suchthat the well-feeding regions are provided on the left and right sidesof the cells as well as the upper and lower sides of the cells. Asexplained with reference to FIG. 5, there is a need to implement therepeating structure, including the well-feeding regions. Byincorporating the NREG1 s for feeding the potential to the wells intothe basic cell structure at the left and right edges of the array, theeffects of the array edge regions can be reduced even when the number ofcolumns is small.

The structure in which the well-feeding regions are also provided on theleft and right sides of the cells can be applied to the NMOS basic cellrepeating structure.

FIG. 24 illustrates the basic structure when the structure in which thewell-feeding regions are also provided on the left and right sides ofthe cells is applied to the structure of FIG. 6 in which the gateelectrodes of the two PMOS transistors in each basic cell are connectedtogether using the POLYG. In such cases as where signals are brought outby passing the METAL1 interconnect lines between the gate/METAL1 contactportions, as with the case of the PMGD1 illustrated in FIG. 18, the cellstructure of FIG. 24 better facilitates the interconnections. It is ofcourse possible to also apply the structure of FIG. 24 to the NMOS basiccells.

While the basic structure of the PMOS array and the basic structure ofthe NMOS array have been described above using similar examples, it willbe appreciated that these possible structures can be used incombination.

FIG. 25 illustrates one example in which the constitution of theinterconnect channels applied up to the METAL2 level of the PMOS arrayillustrated in FIG. 8 is applied to the third interconnect layer METAL3.In FIG. 25, METAL3 indicates the third metal interconnect layer. In FIG.25, the METAL3 is represented by oblique hatching rotated 90 degreesrelative to that of POLYG and enclosed by double-dashed lines.

As previously explained, it is desirable in principle that the METAL1 beused for lateral interconnect lines and the METAL2 for longitudinalinterconnect lines from the viewpoint of ease of interconnections. It istherefore a natural choice to form the METAL3 interconnect lines aslateral interconnect lines crossing at right angles with the METAL2interconnect lines. In the example of FIG. 25, the METAL3 interconnectlines are illustrated as being formed above the METAL1 interconnectlines. They are illustrated as possible interconnect lines, not theactual circuit interconnect lines.

FIG. 26 illustrates another example of the METAL3 interconnect lines.The METAL1 is already present at the gate/METAL1 contacts at the edgesof the POLYGs. As a result, the edges of the POLYGs cannot be used asMETAL1 signal interconnect channels, but when the METAL3 interconnectlines are used, interconnect channels can be formed including the edgeportions of the POLYGs. In this case also, no interconnect lines shouldbe provided above the channel region where an inversion layer is formed.

FIG. 27 illustrates the constitution of interconnect channels to beprovided at a fourth metal interconnect layer METAL4 in the PMOS arrayillustrated in FIG. 8. In FIG. 27, the METAL4 is represented by hatchingwith horizontal and vertical lines, like that used for the METAL2, butenclosed by double-dashed lines.

The METAL4 interconnect channels of FIG. 27 can be formed insubstantially the same manner as the METAL2. In this case also, nointerconnect lines should be provided above the current channels.

FIG. 28 illustrates an example of a bias circuit. The followingillustrates an example of how such a bias circuit can be implementedusing the layout method of the present invention.

In FIG. 28, PMBC1, PMBC2, and PMBC3 are PMOS transistors forming thebias circuit, NMBC1, NMBC2, and NMBC3 are NMOS transistors forming thebias circuit, RB2 is a resistor, PMAC2 and PMAC3 are, for example, thePMOS transistors illustrated in FIG. 12, PB1 is a bias voltage appliedto the PMOS transistors, EN is an enable signal, ENX is an enable signalwhose phase is reversed relative to EN and whose L state triggers thecircuit into operation, NB1 is a bias voltage applied to the NMOStransistors, NDS1 and Vbgr are the nodes designated by the same names inFIG. 12, and NDNS1 is the source node of the NMBC2.

FIG. 29 illustrates a layout example of the PMOS section of the biascircuit of FIG. 28. The method of depicting the layout layers is thesame as that used in the previously illustrated figures. Some of thecorresponding circuit node names are also illustrated. FIG. 29illustrates the layout up to the METAL2 interconnect level, while FIG.30 illustrates the layout only at the METAL1 interconnect level.

The layout example of the bias circuit of FIG. 28 will be described withreference to FIGS. 29 and 30.

The transistors that need matching in FIG. 28 are the PMBC1 and PMBC2forming the transistor pair, and it is also desirable that thecharacteristics of the PMAC2 and PMAC3 are identical to those of thetransistor pair.

In FIG. 29, the PMBC1 and PMBC2 are split, the former into PMBC1A andPMBC1B and the latter into PMBC2A and PMBC2B, and are arranged in acommon centroid configuration. The PMAC2 and PMAC3 are also split inlike manner and arranged in a common centroid configuration. Asillustrated in FIG. 30, since the gate potential is common to theseeight transistors, in each row the gates can be connected together inthe lateral direction by using METAL1 interconnect lines. Further, sincethe gate electrodes are also connected to the drain of the PMBC2, thedrain and gate electrodes of the PMBC2A are connected together by theMETAL1, and the drain and gate electrodes of the PMBC2B are connectedtogether by the METAL1, as illustrated in FIG. 30.

As can be seen from FIG. 30, since the gates of the eight transistorsare connected to the drain by the METAL1, the drain of the PMBC2 acts asan antenna diode. When the drain electrodes of the PMBC2, PMBC1, PMAC2,and PMAC3, respectively arranged in a common centroid configuration, areconnected together by using longitudinally extending METAL2 interconnectlines and laterally extending METAL1 interconnect lines, the circuitinterconnections are completed. Further, since the source potential ofthese transistors is VDD, the sources are connected to the VDD by usinglongitudinally extending METAL2 interconnect lines.

FIG. 29 illustrates the result of the interconnect layout accomplishedbased on the above basic constitution. When a different signal line ispresent above a drain electrode, the signal from the drain electrode isbrought out by using the METAL1 passed between the gate contacts. Thedrain electrode of the PMBC1B and the drain electrode of the PMAC3 b arebrought out in this manner. By connecting the NDS1 and Vbgr to laterallyextending interconnect lines, the circuit can be connected, for example,to the NDS1 illustrated in FIG. 19, to complete the fabrication of thePMOS differential circuit. The circuit portion relating to the Vbgrinterconnect line is not illustrated here, but it can be brought out toa desired position by using longitudinal and lateral interconnect lines.Since there is no need to be concerned about the antenna effect for thedrain interconnects, NDS1, and Vbgr, the configuration such asillustrated in FIG. 29 or 19 is effective.

The PMBC3 is a device for powerdown control for holding the PB1 at theVDD potential. By connecting the drain to the PB1 interconnect line, thesource to VDD, and the gate to EN, the circuit interconnectionsillustrated in FIG. 28 can be accomplished. Since there is no need tomatch the characteristics of the powerdown control device, the device isplaced in the uppermost row of the array, as illustrated in FIGS. 29 and30. In this way, by arranging devices that do not need matching or whosematching priority is low in the peripheral area, and placing the devicesthat most need matching in the center area, the peripheral area of thearray can be used without wasting space, and the devices arranged inthis area can be made to act as dummy devices for the devices placed inthe center area of the array.

FIGS. 29 and 30 have illustrated an implementation example of the layoutby taking as an example the PMOS section of the bias circuit of FIG. 28,but it will be appreciated that the layout of the NMOS section of thebias circuit can be easily implemented in a manner similar to thatillustrated in FIGS. 19 and 29.

With the circuit configuration and layout described above, the offsetvoltage of the operational amplifier can be further reduced. Thispromises to improve the output voltage accuracy of the bandgap circuit.The output voltage accuracy of the regulator circuit using the bandgapcircuit also improves.

With the analog circuit cell array disclosed in the embodiment, theproduction lead time can be greatly reduced, since a high-accuracyanalog circuit can be easily produced by just forming an interconnectionpattern according to the circuit specification.

While the embodiment of the invention has been described above, it willbe easily understood by those skilled in the part that the techniquesdisclosed herein are not limited to the embodiment described above andthat various modifications can be made to it.

All examples and conditional language recited herein are intended forpedagogical purposes to aid the reader in understanding the inventionand the concepts contributed by the inventor to furthering the art, andare to be construed as being without limitation to such specificallyrecited examples and conditions, nor does the organization of suchexamples in the specification relate to a showing of the superiority andinferiority of the invention. Although the embodiments of the presentinvention have been described in detail, it should be understood thatthe various changes, substitutions, and alterations could be made heretowithout departing from the spirit and scope of the invention.

1. An analog circuit cell array including a plurality of transistor cellarranged in an array, each of the transistor cells comprising: a firstsource region, a first channel region, a common drain region, a secondchannel region, and a second source region arranged in sequence oneadjacent to another; and a first gate electrode and a second gateelectrode formed on the first channel region and the second channelregion, respectively, and wherein the first gate electrode and thesecond gate electrode are connected together for use, and the firstsource region and the second source region are connected together foruse.
 2. The analog circuit cell array according to claim 1, wherein theeach transistor cell includes an interconnecting electrode forinterconnecting the first gate electrode and the second gate electrode.3. The analog circuit cell array according to claim 1, wherein the firstgate electrode and the second gate electrode of the each transistor cellextend outwardly of the first channel region and the second channelregion, respectively, and are provided with interconnect contacts onoutwardly extending portions.
 4. The analog circuit cell array accordingto claim 1, comprising a diffusion region, formed in an boundary area ofthe each transistor cell, for feeding a well in the each transistorcell.
 5. The analog circuit cell array according to claim 1, wherein nometal interconnect lines are placed above the first channel region andthe second channel region of any transistor cell configured for use. 6.The analog circuit cell array according to claim 1, wherein theplurality of transistor cells includes PMOS transistor cells and NMOStransistor cells.
 7. The analog circuit cell array according to claim 2,wherein the plurality of transistor cells includes PMOS transistor cellsand NMOS transistor cells.
 8. The analog circuit cell array according toclaim 3, wherein the plurality of transistor cells includes PMOStransistor cells and NMOS transistor cells.
 9. The analog circuit cellarray according to claim 4, wherein the plurality of transistor cellsincludes PMOS transistor cells and NMOS transistor cells.
 10. The analogcircuit cell array according to claim 5, wherein the plurality oftransistor cells includes PMOS transistor cells and NMOS transistorcells.
 11. The analog circuit cell array according to claim 6, whereintransistor cells of identical type are arranged in continuous fashion infour rows and four or more columns.
 12. An analog integrated circuitcomprising: an analog circuit cell array including a plurality oftransistor cell arranged in an array, each of the transistor cellscomprising: a first source region, a first channel region, a commondrain region, a second channel region, and a second source regionarranged in sequence one adjacent to another; and a first gate electrodeand a second gate electrode formed on the first channel region and thesecond channel region, respectively, and wherein the first gateelectrode and the second gate electrode are connected together for use,and the first source region and the second source region are connectedtogether for use.
 13. The analog integrated circuit according to claim12, wherein the plurality of transistor cells include PMOS transistorcells and NMOS transistor cells, transistor cells of identical type arearranged in continuous fashion in four rows and four or more columns;and wherein the analog integrated circuit comprises a transistor pairarranged in a common centroid configuration by using 2×2 transistorcells located in a center area of a section in which the transistorcells of identical type are arranged in continuous fashion in four rowsand four or more columns.
 14. The analog integrated circuit according toclaim 13, comprising a transistor cell connected to the first gateelectrode and the second gate electrode of two transistor cellscontained in the pair arranged in a common centroid configuration.